(a) Technical Field
This invention relates to array architecture of semiconductor Non-Volatile Memory (NVM) and the methods of fabricating the array using the conventional Complimentary-Metal-Oxide-Semiconductor (CMOS) processing technology. In particular, the innovative NOR-type NVM cell strings connect a series of semiconductor NVM cells by field side sub-bitlines. The NOR-type flash array consisting of such multi-strings has cell area density at least as high as those in the conventional NAND-type flash array. While on the benefit of increasing the cell area density, the disclosed invention preserves the typical NOR-type flash advantages over NAND-type flash on fast read/write speed and low operation voltages.
(b) Description of the Related Art
Semiconductor Non-Volatile Memory (NVM), and particularly Electrically Erasable, Programmable Read-Only Memories (EEPROM), exhibit wide spread applicability in a range of electronic equipments from computers, to telecommunication hardware, to consumer appliances. In general, EEPROM serves a niche in the NVM space as a mechanism for storing firmware and data that can be kept even with power off and can be altered as needed.
Data is stored in an EEPROM cell by modulating its threshold voltage (device on/off voltage) of the Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) through the injection of charge carriers into the charge-storage layer from the substrate of the MOSFET. For example, with respect to an N-channel MOSFET, an accumulation of electrons in the floating gate, or in a dielectric layer, or nano-crystals above the FET channel region, causes the MOSFET to exhibit a relatively high threshold voltage.
Flash EEPROM may be regarded as a specifically configured EEPROM into cell array that may be erased only on a global or sector-by-sector basis. Flash NVM arrays are also categorized as NOR flash and NAND flash according to the configurations of the memory cell connections in the flash arrays. The “NOR” flash array connects NVM cells in parallel, where all the source electrodes of the NVM cell are connected to a common ground 12 and all the drain electrodes of the NVM cells are connected to multiple bitlines, respectively. As shown the cell schematic for an “M×N” NOR flash array in FIG. 1, each wordline running in x-direction contains “M” NVM cells with their individual drain electrodes connected to “M” bitlines and each bitline running in y-direction is attached with “N” drain electrodes of the NVM cells. All the source electrodes of the NVM cells in the array are connected to a single common ground 12. When a wordline is selected the entire “M” NVM cells under the selected wordline are activated. On the other hand, the NVM cells under the unselected wordlines in the array are electrically detached from the “M” bitlines. The electrical responses at the drain electrodes of the selected “M” NVM cells can be detected through their attached “M” bitlines. Since the electrical biases and signals are directly applied to electrodes of the selected NVM cells in NOR-type flash array. In general, the read and write access speed are faster and operation voltages are lower for NOR-type flash in comparison with its counter part, NAND-type flash array.
The NAND type flash array connects the NVM cells in series. Unlike the NOR type array with the configuration of source electrode-to-source electrode connection and drain electrode-to-drain electrode connection, NAND type array link the drain electrode of an NVM cell to the source electrode of its next neighboring cell. Usually, the numbers of NVM cells linked in one single NAND string are from 8 cells to 32 cells depending on the generations of the process technology nodes. In FIG. 2 the schematic for an “M×N” NAND flash array, the array contains “M” NAND cell strings and each NAND cell string contains “p” NVM cells (p=8˜32) and one selection gate to connect the string to the main bitline. Each bitline has “q” NAND strings attached. Thus the total NVM cells attached to a single main bitline is p*q=N for an “M×N” NAND array. Since the source electrode and the drain electrode of NVM cells are overlapped each others in the NAND cell string the NVM cells have no contacts in between the linked NVM cells except one contact 11 placed at the end of the cell string for connecting the NAND string to the main bitline. Usually, a single main bitline connects several NAND strings in y-direction and common source lines 12 run in x-direction in the NAND flash array. In contrast, each NVM cell in NOR-type array does have one contact 11 for connecting a single cell's drain electrode to the main bitline. A NOR-type flash array is equivalently to a NAND-type array with p=1. Typically, the NOR-type NVM cell sizes including the area for a single contact 11 in a NOR flash array are 9˜10 F2 and the NAND-type NVM cell sizes without a contact area in a NAND flash array are 4˜5 F2, respectively, where F is minimum feature size for a process technology node. Therefore, the chip cell array areas for NAND type flash arrays are smaller than the NOR type flash arrays (˜40% to ˜50% smaller) for the same memory size and the same process technology node. In term, the smaller cell array areas for NAND flash have the advantage of lower manufacturing cost for the same bit storage capacity.
On the other hand, to access a NAND flash cell in a NAND string requires sufficient high voltage applied to the control gates of the unselected NVM cells for passing the electrical biases to the source electrode and drain electrode of the selected NVM cell. The access time including the time required for charging the unselected gates to a sufficient high voltage to turn on the NVM cells for passing electrical biases in the NAND string is long, typically, several tens of microseconds compared with a typical NOR flash access time of several tens of nanoseconds. For random read access, NOR flash is several hundred times faster than NAND flash.
For the programming methods, NOR flash usually applies Hot Carrier Injection (HCI) and NAND flash usually applies Fowler-Nordheim (F/N) tunneling, respectively. The F/N tunneling requires higher applied voltages and longer pulse duration to gain the same amount of threshold voltage shifts for semiconductor NVM cells in comparison with HCI. Typically, the voltages for F/N tunneling are from 17V to 22V with pulse durations of hundreds of μs to tens of ms versus from 3V to 10V with pulse durations of hundreds of ns to tens of μs for HCI. Therefore, the program efficiency per pulse shot for NOR flash is much higher than NAND flash.
In this invention, we disclose an innovative NOR-type flash array by applying field side sub-bitlines for connecting the NVM cells into an NOR-type cell string. While having higher performance on read/write speed and low operation voltages, the new NOR flash arrays have a compatible cell area density as those in NAND flash array. The methods of fabricating the new type of Field Side sub-bitline NOR (FSNOR) flash using the conventional Metal-Oxide-Semiconductor-Field-Effect-Transistor (MOSFET) process technology are also disclosed.